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Texas A & M University – Commerce Computer Architecture Question Discussion

Texas A & M University – Commerce Computer Architecture Question Discussion

Question Description

I’m working on a computer science exercise and need an explanation to help me learn.

  1. Design an expanding opcode to allow all the following to be encoded in a 32-bit instruction:15 instructions with two 12-bit addresses and one 4-bit register number650 instructions with one 12-bit address and one 4-bit register number80 instructions with no addresses or registers
  2. Convert the following formulas from infix to reverse Polish notation.a. A+ B + C +D− Eb. (A− B) × (C + D) + Ec. (A × B) + (C × D) − Ed. (A − B) × (((C −D×E) / F) / G) ×H
  3. Convert the following infix formula to reverse Polish notation and generate IJVM code
    to evaluate it: (5 × 2 + 7) − (4 / 2 + 1)
  4. For the 16-bit binary number 1001 0101 1100 0011, show the effect of:
    a. A right shift of 4 bits with zero fill.
    b. A right shift of 4 bits with sign extension.
    c. A left shift of 4 bits.
    d. A left rotate of 4 bits.
    e. A right rotate of 4 bits.
  5. A computer uses DMA to read from its disk. The disk has 64 512-byte sectors per track. The disk rotation time is 16 msec. The bus is 16 bits wide, and bus transfers take 500 nsec each. The average CPU instruction requires two bus cycles. How much is the CPU slowed down by DMA?

Attached is the supporting lecture slide.

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